HAL SDRAM types migration

This section provides information about the HAL SDRAM types migration.

HAL SDRAM type definition

HAL SDRAM callback ID type definition

HAL1

HAL2 

typedef enum
{
  HAL_SDRAM_MSP_INIT_CB_ID,
  HAL_SDRAM_MSP_DEINIT_CB_ID,
  HAL_SDRAM_REFRESH_ERR_CB_ID,
  HAL_SDRAM_DMA_XFER_CPLT_CB_ID,
  HAL_SDRAM_DMA_XFER_ERR_CB_ID,
} HAL_SDRAM_CallbackIDTypeDef;

Note

  • HAL_SDRAM_REFRESH_ERR_CB_ID: Use directly HAL_SDRAM_RegisterRefreshErrorCallback().

  • HAL_SDRAM_DMA_XFER_CPLT_CB_ID and HAL_SDRAM_DMA_XFER_ERR_CB_ID are removed from HAL2 and the Read/Write APIs are no longer available in HAL SDRAM, use HAL DMA APIs instead.

Related concept: Remove MspInit and MspDeInit callbacks

HAL SDRAM state type definition

In HAL2, SDRAM is managed through two distinct state machines:

  • Global state machine: hal_sdram_state_t

  • Device state machine: hal_sdram_device_state_t

HAL1

HAL2 

typedef enum
{
  HAL_SDRAM_STATE_RESET, /* Not yet initialized */
  HAL_SDRAM_STATE_READY, /* Ready for use */
  HAL_SDRAM_STATE_BUSY, /* Process is ongoing */
  HAL_SDRAM_STATE_ERROR, /* Error state */
  HAL_SDRAM_STATE_WRITE_PROTECTED, /* Write protected */
  HAL_SDRAM_STATE_PRECHARGED, /* Device precharged */
} HAL_SDRAM_StateTypeDef;

typedef enum
{
  HAL_SDRAM_STATE_RESET, /* SDRAM not yet initialized */
  HAL_SDRAM_STATE_INIT, /* SDRAM not yet configured */
  HAL_SDRAM_STATE_CONFIGURED, /* SDRAM memory common configured */
} hal_sdram_state_t;

typedef enum
{
  HAL_SDRAM_DEVICE_STATE_RESET, /* Device not yet configured */
  HAL_SDRAM_DEVICE_STATE_MEMORY_CONFIGURED, /* Device configured */
  HAL_SDRAM_DEVICE_STATE_MEMORY_IDLE, /* Device ready to use */
  HAL_SDRAM_DEVICE_STATE_ACTIVE, /* Device process is ongoing */
} hal_sdram_device_state_t;

Note

  • HAL_SDRAM_STATE_BUSY is replaced with HAL_SDRAM_DEVICE_STATE_ACTIVE for each device.

  • HAL_SDRAM_STATE_ERROR is removed (No more Read/Write APIs use in HAL SDRAM driver).

  • HAL_SDRAM_STATE_WRITE_PROTECTED is removed, no more state to reflect the SDRAM write protection instead use the function HAL_SDRAM_IsEnabledWriteProtection() to know if the sdram is write protected.

  • HAL_SDRAM_STATE_READY is replaced with HAL_SDRAM_DEVICE_STATE_MEMORY_IDLE for each device.

  • HAL_SDRAM_STATE_PRECHARGED is removed, same use as HAL_SDRAM_DEVICE_STATE_MEMORY_IDLE.

Related concepts:

HAL SDRAM type definition

HAL SDRAM initialization and timing type definition

HAL1

HAL2 

typedef struct
{
  /* Start of memory configuration */
  uint32_t SDBank;
  uint32_t ColumnBitsNumber;
  uint32_t RowBitsNumber;
  uint32_t MemoryDataWidth;
  uint32_t InternalBankNumber;
  uint32_t CASLatency;
  /* End of memory configuration */



  /* Start of common configuration */
  /* ------------- */
  uint32_t WriteProtection;
  uint32_t SDClockPeriod; /* in clock cycle */
  uint32_t ReadBurst;
  uint32_t ReadPipeDelay;
} FMC_SDRAM_InitTypeDef;

typedef struct
{
  uint32_t LoadToActiveDelay;
  uint32_t ExitSelfRefreshDelay;
  uint32_t SelfRefreshTime;
  uint32_t RowCycleDelay;
  uint32_t WriteRecoveryTime;
  uint32_t RPDelay;
  uint32_t RCDDelay;
} FMC_SDRAM_TimingTypeDef;

typedef struct
{
  /* Start of memory configuration */
  /* SDBank passed as device in HAL2 */
  hal_sdram_column_addr_width_t column_address_width;
  hal_sdram_row_addr_width_t    row_address_width;
  hal_sdram_memory_bus_width_t memory_bus_width;
  hal_sdram_intern_banks_number_t intern_banks_num;
  hal_sdram_cas_latency_t cas_latency;
} hal_sdram_memory_config_t;

typedef struct
{
  /* WriteProtection removed from Config
     use "HAL_SDRAM_EnableWriteProtection()",
         "HAL_SDRAM_DisableWriteProtection()" */
  uint32_t sdram_clock_period_nsec; /* in ns */
  uint32_t ReadBurst; /* used in some board */
  hal_sdram_read_pipe_delay_t read_pipe_delay;



  /* see FMC_SDRAM_TimingTypeDef */
  uint32_t load_to_active_delay_nsec;
  uint32_t exit_self_refresh_delay_nsec;
  uint32_t self_refresh_time_nsec;
  uint32_t row_cycle_delay_nsec;
  uint32_t write_recovery_time_nsec;
  uint32_t precharge_command_delay_nsec;
  uint32_t activate_rd_wr_command_delay_nsec;
  uint32_t rows_number;
} hal_sdram_common_config_t;

Related type: HAL SDRAM initialization and timing type definition

Related use case: HAL SDRAM initialization and configuration functions migration

HAL SDRAM handle type definition

HAL1

HAL2 

typedef SDRAM_HandleTypeDef;

typedef hal_sdram_handle_t;

Related concept: Replaced TypeDef suffix with _t in type names

HAL SDRAM FMC command type definition

The CommandTarget represent the device that is targeted in HAL2. It is passed as:

HAL1

HAL2

The CommandTarget ( FMC_SDRAM_CMD_TARGET_BANK1, FMC_SDRAM_CMD_TARGET_BANK2) is set in the command structure.

The Device ( HAL_SDRAM_DEVICE1, HAL_SDRAM_DEVICE2) replace the CommandTarget and passed as API parameter to HAL_SDRAM_SendCommand(). 

typedef struct
{
  uint32_t CommandMode;
  uint32_t CommandTarget;
  uint32_t AutoRefreshNumber;
  uint32_t ModeRegisterDefinition;
} FMC_SDRAM_CommandTypeDef;

typedef struct
{
  hal_sdram_command_code_t command;
  /* CommandTarget is passed as API parameter */
  uint32_t parameter;
  /* ------------- */
} hal_sdram_command_t;

Note

  • See FMC command mode constant definition, FMC command target constant definition.

  • In HAL1, the AutoRefreshNumber and ModeRegisterDefinition parameters are given explicitly in the structure. These parameters are used exclusively and respectively in HAL_SDRAM_COMMAND_AUTOREFRESH and HAL_SDRAM_COMMAND_LOAD.

  • In HAL2, these parameters are replaced by one single parameter that represent AutoRefreshNumber in case of HAL_SDRAM_COMMAND_AUTOREFRESH and ModeRegisterDefinition in case of HAL_SDRAM_COMMAND_LOAD.

Related use case: Use case: Command process operation Related function: HAL SDRAM sends command

HAL SDRAM constant definition

FMC command mode constant definition

HAL1

HAL2 



#define FMC_SDRAM_CMD_NORMAL_MODE
#define FMC_SDRAM_CMD_CLK_ENABLE
#define FMC_SDRAM_CMD_PALL
#define FMC_SDRAM_CMD_AUTOREFRESH_MODE
#define FMC_SDRAM_CMD_LOAD_MODE
#define FMC_SDRAM_CMD_SELFREFRESH_MODE
#define FMC_SDRAM_CMD_POWERDOWN_MODE

typedef enum
{
  HAL_SDRAM_COMMAND_NORMAL
  HAL_SDRAM_COMMAND_CLK_ENABLE //Exists only in some series
  HAL_SDRAM_COMMAND_PALL
  HAL_SDRAM_COMMAND_AUTOREFRESH
  HAL_SDRAM_COMMAND_LOAD
  HAL_SDRAM_COMMAND_SELFREFRESH
  HAL_SDRAM_COMMAND_POWERDOWN
} hal_sdram_command_code_t;

Related use case: Use case: Command process operation

FMC command target constant definition

HAL1

HAL2 



#define FMC_SDRAM_CMD_TARGET_BANK1
#define FMC_SDRAM_CMD_TARGET_BANK2
#define FMC_SDRAM_CMD_TARGET_BANK1_2

typedef enum
{
  HAL_SDRAM_DEVICE1
  HAL_SDRAM_DEVICE2
  /* ------------ */
} hal_sdram_device_t;

Related use case: Other HAL SDRAM changes

FMC column bits constant definition

HAL1

HAL2 



#define FMC_SDRAM_COLUMN_BITS_NUM_8
#define FMC_SDRAM_COLUMN_BITS_NUM_9
#define FMC_SDRAM_COLUMN_BITS_NUM_10
#define FMC_SDRAM_COLUMN_BITS_NUM_11

typedef enum
{
  HAL_SDRAM_COLUMN_ADDR_WIDTH_8_BIT,
  HAL_SDRAM_COLUMN_ADDR_WIDTH_9_BIT,
  HAL_SDRAM_COLUMN_ADDR_WIDTH_10_BIT,
  HAL_SDRAM_COLUMN_ADDR_WIDTH_11_BIT,
} hal_sdram_column_addr_width_t;

FMC row bits constant definition

HAL1

HAL2 



#define FMC_SDRAM_ROW_BITS_NUM_11
#define FMC_SDRAM_ROW_BITS_NUM_12
#define FMC_SDRAM_ROW_BITS_NUM_13

typedef enum
{
  HAL_SDRAM_ROW_ADDR_WIDTH_11_BIT,
  HAL_SDRAM_ROW_ADDR_WIDTH_12_BIT,
  HAL_SDRAM_ROW_ADDR_WIDTH_13_BIT,
} hal_sdram_row_addr_width_t;

FMC SDRAM CAS latency constant definition

HAL1

HAL2 




#define FMC_SDRAM_CAS_LATENCY_1
#define FMC_SDRAM_CAS_LATENCY_2
#define FMC_SDRAM_CAS_LATENCY_3

typedef enum
{
  HAL_SDRAM_CAS_LATENCY_DISABLED,
  HAL_SDRAM_CAS_LATENCY_1_CYCLE,
  HAL_SDRAM_CAS_LATENCY_2_CYCLE,
  HAL_SDRAM_CAS_LATENCY_3_CYCLE
} hal_sdram_cas_latency_t;

FMC SDRAM write protection disable/enable constant definition

HAL1

HAL2 

#define FMC_SDRAM_WRITE_PROTECTION_DISABLE
#define FMC_SDRAM_WRITE_PROTECTION_ENABLE

Removed from HAL2: write protection is no longer set in the configuration structure.

FMC SDRAM read pipe delay constant definition

HAL1

HAL2 



#define FMC_SDRAM_RPIPE_DELAY_0
#define FMC_SDRAM_RPIPE_DELAY_1
#define FMC_SDRAM_RPIPE_DELAY_2

typedef enum
{
  HAL_SDRAM_READ_PIPE_DELAY_0_CYCLE,
  HAL_SDRAM_READ_PIPE_DELAY_1_CYCLE,
  HAL_SDRAM_READ_PIPE_DELAY_2_CYCLE
} hal_sdram_read_pipe_delay_t;

HAL SDRAM pointer definition

HAL SDRAM callback type definition

HAL1

HAL2

pSDRAM_CallbackTypeDef

hal_sdram_cb_t

Related concept: Replaced TypeDef suffix with _t in type names

HAL SDRAM callback DMA type definition

HAL1

HAL2

pSDRAM_DmaCallbackTypeDef

Removed: No more Read/Write APIs use in HAL SDRAM driver.

Related concept: Replaced TypeDef suffix with _t in type names